1. Field of the Invention
This invention relates to a semiconductor device of, e.g., a ball grid array (BGA) type, in which a semiconductor chip is connected, through flip chip bonding, to a mounting substrate manufactured by the same method as that for an organic printed wiring board, and a method for manufacturing the same.
2. Description of the Related Art
Generally, a mounting substrate to which the semiconductor chip is connected through flip chip bonding is manufactured by the same method as that for an organic printed wiring board. The mounting substrate is formed of wiring layers the number of which ranges from two to a dozen or so depending on purposes. However, the thickness of the mounting substrate is about 0.5 to 2.0 m even if there are a dozen wiring layers or so. Accordingly, the mounting substrate is very vulnerable to external force or stress caused by a difference in coefficients of thermal expansion between materials of different kinds and is easily warped. Outside dimensions of the mounting substrate greatly vary depending on a size of a semiconductor chip to be mounted on the mounting substrate, the number of external terminals, and a way of arrangement of the external terminals, e.g., a full grid or a peripheral grid. To take an example, because of lighter weight and thinner formation requirements, the outside dimensions of the mounting substrate are 45 to 50 mmsquare and the thickness thereof is about 1.0 to 2.5 mm in a case where a semiconductor chip is about 17 to 20 mmsquare, the number of pad electrodes of the chip is 2000 to 3000, and the way of arrangement of 1800 to 2000 external terminals (bumps) necessary to be disposed on the mounting substrate is a full grid.
First, a conventional semiconductor device will be described with reference to Japanese Patent Laid-Open Publication No. 2000-323624 and FIGS. 14a and 14b. FIG. 14a is a plan view of a conventional semiconductor device 200, described in, e.g., Japanese Patent Laid-Open Publication No. 2000-323624, in a state in which a lid 231 is removed, and FIG. 14b is a sectional view taken along the line E-E′ of FIG. 14a in a state in which the lid 231 is attached. In this semiconductor device 200, a semiconductor chip 220 is connected to amounting substrate 210 with a thickness of about 1 mm through flip chip bonding, and a gap therebetween is filled with an underfill resin 240 to be cured. A stiffener 230 is bonded to the mounting substrate 210 so as to surround the semiconductor chip 220, and the lid 231 is fixed to a backside of the semiconductor chip 220 and to an end surface of the stiffener 230 with a conductive adhesive 243. In addition, a space 247 is formed between the stiffener 230 and side faces of the semiconductor chip 220.
Next, an outline of a method for manufacturing the conventional semiconductor device 200 will be described with reference to FIGS. 15a to 15g. First, the above-described mounting substrate 210, the semiconductor chip 220, the stiffener 230, the underfill resin 240, an epoxy resin adhesive 242, the conductive adhesive 243, and the lid 231 are prepared, and a wiring board diagram of FIG. 15a is set on a stage (not shown) of a screen printer or of a dispenser. Next, the epoxy resin adhesive 242 with a thermal expansion coefficient of 16 to 22 ppm is applied to a peripheral portion of the mounting substrate 210 by means of the screen printer or the dispenser. Thereafter, the stiffener 230 is mounted thereon, and the epoxy resin adhesive 242 is cured at a predetermined temperature (around 100 to 160° C.) (FIG. 15b). Subsequently, bump electrodes 222 formed on pads 221 of the semiconductor chip 220 and lands 211 of the mounting semiconductor substrate 210 are aligned with each other by a flip chip mounter (not shown), and then melted to be connected at a temperature of around 250° C. in the case of a low-melting alloy, e.g., Pb-free solder (FIG. 15c).
In other methods, as a method of connecting the pads 221 of the semiconductor chip 220 and the lands 211 of the mounting substrate 210, there is a method in which materials of joined surfaces include Au and Al, and Au and Au, respectively, and the pads 221 and the lands 211 are connected by applying an ultrasonic wave while heating them. In this case, real curing of the epoxy resin adhesive 242 to bond the stiffener 230 to the mounting substrate 210 is carried out in a separate step. Next, in order to secure adhesive strength of the mounting substrate 210 and the semiconductor chip 220, a gap of about several 100 μm therebetween is filled with the underfill resin 240 which has a thermal expansion coefficient of about 32 ppm and flowability, using the dispenser or the like by utilizing capillary. Then, the underfill resin 240 is cured at a temperature of about 100° C. (FIG. 15d).
Next, the conductive adhesive 243 with a thermal expansion coefficient of 16 to 22 ppm is attached onto the end surface of the stiffener 230 and onto the backside of the semiconductor chip 220 by coating or a printing method (FIG. 15e). Subsequently, the lid 231 is aligned with the stiffener 230 and mounted thereon by applying a proper load. Further, in this state, the conductive adhesive 243 is cured at a temperature of about 150 to 170° C. (FIG. 15f). A batch-processing method in an oven or a general method of continuously putting materials into a belt furnace to cure the materials is applicable for the curing method.
Lastly, solder bumps 213 and external terminals, are bonded to the lands 212 of the mounting substrate 210 by a general method (FIG. 15g). In the conventional semiconductor device 200, in a state at a room temperature and immediately after the solder bumps 213 are bonded to the lands 212 of the mounting substrate 210, as shown in FIG. 16a for example, a portion of the mounting substrate 210 opposite the semiconductor chip 220 is pulled to a semiconductor chip 220 side by about 100 μm form a convex-shape on a chip mounting surface side.
FIG. 16a is a view schematically showing a state of warpage in the mounting substrate 210 when the semiconductor device 200 is at a room temperature of 20° C., and FIGS. 16b and 16c are views schematically showing state of warpage in the mounting substrate 210 when the semiconductor device 200 is at a low temperature of −45° C. and at a high temperature of 150° C., respectively. As shown in FIG. 16a, the conventional semiconductor device 200 is in a state of being convex to the chip side by about 100 μm at the room temperature of 20° C. When the semiconductor device 200 is cooled to −45° C. from this state, the amount of warpage is increased to 180 μm as shown in FIG. 16b. When the temperature is once returned to the room temperature, and then the semiconductor device 200 is heated to 150° C., the amount of warpage is reduced to about 50 μm as shown in FIG. 16c. Accordingly, in the conventional semiconductor device 200, if a temperature cycling between the low temperature state of −45° C. and the high temperature state of 150° C. is repeated several hundred to several thousand times, cracks may occur in the bump electrodes 222 which join the pads 221 of the semiconductor chip 220 to the lands 211 of the mounting substrate 210, and detachment may also occur in joined interfaces.
A reason for the occurrence of cracks in the solder bumps and for the detachment in the joined interfaces between the pads and the lands can be presumed as follows. FIG. 17 is an enlarged schematic view of the vicinity of one of the bump electrodes 222 to explain the reason. Hereinafter, the description will be made with reference to FIG. 17. Stress with an in-plane direction generated by the thermal expansion coefficient difference between the mounting substrate 210 and the semiconductor chip 220 is absorbed with the underfill resin 240 filled into the gap. However, the contraction of the underfill resin 240 brings a state in which the bump electrode 222 is pulled toward the semiconductor chip 220, and at the same time force in a vertical direction to the surface of the semiconductor chip 220 is applied. If the temperature cycling is repeated in this state, the mounting substrate 210 including the semiconductor chip 220 repeatedly moves between a convex shape and in a flat shape, and thus stresses of tension and compression are repeated in the connected portion of the bump electrode 222 with the pad 221 or in the connected portion of the mounting substrate 210 with the land 211. Consequently, it can be presumed that a crack 217 occurs in the bump electrode 222 and detachment 218 occurs in the joined interface, thus leading to destruction.
In the semiconductor device 200 manufactured by the aforementioned method, the pads 221 of the semiconductor chip 220 with a thickness of 0.7 mm are connected to the wiring electrodes 211 of the resin mounting substrate 210 with a thickness of 0.5 to 2.0 mm through the bump electrodes 222, and secured by the underfill resin 240 for reinforcing the connected portions. In addition, the stiffener 230 with a thickness of about 0.5 to 1.0 mm is bonded to the resin mounting substrate 210 so as to surround the semiconductor chip 220, thereby increasing the flatness and the strength of the resin mounting substrate 210. In this state, the lid 243 with a thickness of 0.5 to 1.0 mm for protecting the semiconductor chip 220 is mounted, thus configuring the semiconductor device 200.
The warpage in the substrate as shown in FIG. 16a occurs in the mounting substrate 210 of the semiconductor device 200 constituted of the aforementioned components at the room temperature. This view is a sectional view taken along the line E-E′ of FIG. 14a. A portion directly facing the semiconductor chip 220 is pulled toward the semiconductor chip 220 by the contraction of the underfill resin 240 to be in a convex state on the chip mounting surface side. A portion directly bonded to the stiffener 230 is also deformed to be slightly convex on the chip mounting surface side. In other words, deformation of two-stage shapes occurs.
If the thermal expansion coefficient of the underfill resin 240 is reduced to about 16 to 22 ppm, the phenomenon that the portion directly facing the semiconductor chip 220 is pulled to be convex may be suppressed to a certain extent. However, it is difficult to greatly reduce the amount of warpage in the mounting substrate. To reduce the thermal expansion coefficient of the underfill resin 240, a large amount of silica filler or the like is generally mixed. However, this causes an increase in the viscosity of the resin. Consequently, voids are generated in the underfill resin 240 in a region where the mounting substrate 210 and the semiconductor chip 220 face each other, and thereby the detachment phenomenon easily occurs. Therefore, it was difficult to reduce the thermal expansion coefficient to 32 ppm or lower. That is, there is a trade-off relation between the thermal expansion coefficient of the underfill resin 240 and the viscosity thereof, in which filler such as silica or alumina only needs to be mixed by a large amount in order to reduce the thermal expansion coefficient, but a larger amount of the mixed filler causes a higher viscosity.
Japanese Patent Laid-Open Publication No. 2000-260820 discloses a semiconductor device configured in such a manner that a semiconductor chip is connected to a wiring pattern surface of a mounting substrate; a first sealant (underfill resin) is injected into a gap therebetween at 60 to 120° C. and then cured at 140 to 170° C.; and thereafter side faces of the chip are sealed by a second sealant (well-known fillet material). In this semiconductor device, the first sealant is present in the gap between the chip and the substrate, and the second sealant is formed in a fillet shape on the side faces of the semiconductor chip.
Furthermore, Japanese Patent Laid-Open Publication No. 2000-349203 discloses a semiconductor device configured in such a manner that a semiconductor chip is connected to an interposer substrate through flip chip bonding; a gap between the interposer substrate and the semiconductor chip, and a corresponding portion to the aforementioned stiffener are integrally filled with resin by transfer molding; and a heat spreader (equivalent to the lid) is mounted thereon.
It has now been discovered that, in the conventional semiconductor device, in order to prevent the destruction of the bumps for solder-connecting the materials different in coefficients of thermal expansion, such as the mounting substrate made of an organic resin substrate and the semiconductor chip including, e.g., silicon, a gap between the semiconductor chip and the mounting substrate is filled with the underfill resin with a high thermal expansion coefficient and with a high elastic modulus, thereby reducing stress caused by the difference in thermal expansion coefficients therebetween. However, because of great differences in thermal expansion coefficient and elastic modulus between the materials, at the end of the manufacturing process, the region where the mounting substrate and the semiconductor chip face each other through the underfill resin is in a warped state due to the occurrence of stress to be pulled to the semiconductor chip side. Accordingly, an increased amount of warpage causes a problem that a solder connection failure easily occurs in a warped portion when the semiconductor device is mounted on a circuit board or the like by soldering. Additionally, as for the semiconductor device itself, there is no problem in a state of a room temperature with small fluctuation in a range of about 5° C. to 35° C. However, if a low temperature and a high temperature is repeated like the temperature cycling, there is a problem that the warpage in the mounting substrate causes cracks in the solder bumps for connecting the pads of the semiconductor chip to the lands of the mounting substrate, and detachment in the joined interfaces.
Furthermore, for example, even in the structure in which the first sealant is present in the gap between the chip and the substrate, and the second sealant is formed in a fillet shape on the side faces, it is impossible to completely prevent the contraction of the first sealant and the substrate directly facing the chip. Further, in the case of the structure in which the sealing resin with a large filler content is injected as the underfill resin to fill a gap between the interposer substrate and the semiconductor chip by transfer molding, because of the high viscosity of the resin, voids are easily generated in the gap between the interposer substrate and the semiconductor chip, thereby causing problems leading to loss of reliability, such as the occurrence of cracks and detachment.